This invention relates to semiconductor devices, specifically to the gate critical dimension control and endcap improvement through use of dummy patterns.
The existence of pattern effect in films has been well known. There is a problem that a “micro-loading effect” occurs due to a difference in pattern density and degrades the uniformity of pattern sizes. The micro-loading effect pertains to a phenomenon occurring upon simultaneously etching or polishing a pattern of a higher density and a pattern of a lower density. Due to a difference in the etching/polishing rate of a film from one location to another, the amount of reaction produced by the etching/polishing becomes locally dense or sparse, and the convection of a large amount of reaction products by etching with a low volatility causes a non-uniformity in the etching rate. Large variations in effective pattern density have been shown to result in significant and undesirable effects such as pattern dimension deviation and thickness variation.
To counteract this effect, a layout design step known as dummy fill, where the circuit layout is modified and dummy patterns are added to locations with low pattern density, was developed. The adding of dummy patterns helps to achieve uniform effective pattern density across the wafer, therefore avoiding problems.
Conventionally, such dummy patterns are left in place. In the case dummy patterns are conductive, they form parasitic capacitance with the interlayer metal wiring. The parasitic capacitance contributes to the RC time delay due to charging and discharging time. The scaling scheme of interlayer dielectrics (ILD) and higher operation frequency for advanced processes will cause severe performance degradation due to unwanted parasitic capacitance. At the present stage of development of the integrated circuit art, there is an increasing demand in the field of digital integrated circuits for faster switching circuits. As the switching demands of the integrated circuits go into higher frequency, the slowing effect produced by parasitic capacitance becomes an increasing problem.
Since dummy patterns are not removed, they cannot be formed in an active region, or oxide defined (OD) region. Leftover dummy patterns not only increase parasitic capacitance and degrade device performance, but also affect the subsequent processes. One of the conventional solutions is to place dummy patterns surrounding, but not in, the active regions. Not being able to be placed in desired regions, the effect of the dummy patterns is significantly limited. Such an arrangement also increases the difficulty of fine-tuning the dummy patterns. There were also efforts made to put dummy patterns into dummy active regions, or regions having neither an oxide nor an active device. However, the results have generally not proven satisfactory.
There is another effect that also affects the semiconductor process. When two devices are too close to each other, “optical proximity effects” occur. Optical proximity effects are due to light diffraction and interference between closely spaced features on the reticle resulting in the widths of lines in the lithographic image being affected by other nearby features. One component of the proximity effect is optical interaction among neighboring features; other components arise from similar mechanisms in the resist and etch processes. Thus, under the present restricted design rule (RDR) environment, when a special layout design of polysilicon (“poly”) gates includes poly gates disposed in vertical and horizontal directions (from a top view perspective), an area penalty is needed to avoid undesirable side effects in lithography, process, and device. For example, as shown in FIGS. 15 and 17, the minimum spacing between the tip of a vertical poly line endcap 87 and an adjacent horizontal poly line 80c has typically been a minimum of about 100 nm for lithography to be used to form a satisfactory poly line. In another example, as further shown in FIGS. 15 and 17, a poly endcap 87 has been required to extend a minimum of 80 nm to also avoid optical proximity effects.
The micro-loading and proximity effects affect the gate formation of metal-oxide-semiconductor (MOS) devices. The critical dimension, or the gate length of a MOS device, may deviate significantly from design. For example, if an 80 nm gate length is desired, when the critical dimension of a MOS device in a dense device area is on target at 80 nm, the critical dimension of a MOS device in an isolated device area may reach around 110 nm, or 30 nm more than the target value in certain cases. Also the deviations for nMOS and pMOS gates are different, causing N/P ratio mismatching and complicating circuit design. Furthermore, the spacing limitations for vertical and horizontal poly lines mentioned above make improving total gate density difficult.
Lack of process control in gate formation also causes endcap problems. FIG. 1 illustrates a conventional layout comprising two MOS devices. Gate 2 and active region 6 form a first device 8. Gate 4 and active region 7 form a second device 5. Gates 2 and 4 have endcaps 9 and 11 respectively, extending outside active regions 6 and 7. Due to the micro loading or proximity effects, endcaps 9 and 11 may be longer or shorter than designed. When endcaps 9 and 11 are longer than designed, polysilicon (“poly”) gates 2 and 4 may be shorted, causing device failure. Conversely, problems may also occur if endcaps 9 and 11 are shorter than designed, as shown in FIG. 2. If endcap 9 or 11 is recessed into the active region 6 or 7, it cannot effectively control the channel of the device and shut off the MOS device. As a consequence, a significant leakage current may exist between the source and drain of devices 8 and 5.